1. Field of the Invention
The present invention relates generally to the dispatch of instructions in a processing system having multiple execution units. More specifically, a system having multiple instruction buffers is provided wherein instructions are defined as dependent, independent or dependent on an unavailable resource. These instructions are executed sequentially or in parallel depending upon their definition and relationship to other instructions.
2. Description of Related Art
It is currently known to have processing systems with multiple execution units therein. A great majority of the conventional systems include multiple special purpose execution units for performing such operations as add, store, load, subtract, multiply, branch, and the like. In order to solve the problems associated with instruction dependencies, conventional systems place the specific instructions in a buffer associated with the corresponding special purpose execution unit. For example, a load operation will be placed in a buffer associated with the load unit, and so on. If instruction dependencies are present conventional systems merely hold the later instruction, which depends on the outcome of a previous instruction. Once the previous instruction has executed the later dependent instruction is allowed to execute on the specific execution unit. It should be noted that in conventional systems shifting of instructions may occur between various buffers associated with various execution units, but this shifting depends on the relationship between the type of instruction and the particular execution unit which can execute that type of instruction. That is, a load instruction may be shifted to a buffer associated with the load execution unit. Also, these prior art, multiple execution unit systems generally execute instruction in an out of order sequence, in contrast to the present invention which preserves the order of the instructions.
U.S. Pat. No. 5,133,077 shows multiple distinct execution, each having responsibility for specific types of instructions. Therefore, each instruction must be stored in a specific buffer that is associated with one of the execution units, based on the type of instruction. These instructions cannot be shifted to another buffer associated with another execution unit, because they are specific to a certain type of execution unit. Thus, when instruction dependencies are discovered this system has no alternative, but to hold the later dependent instruction until the previous instruction, which the held instruction is dependent upon, has completed execution.
U.S. Pat. No. 4,837,678 discusses a system including an instruction sequencer including a shifting circuit that receives instructions and shifts them based on the type of instruction and which execution unit is required to execute the instruction (column 11, lines 8-30), not dependencies between instructions.
U.S. Pat. No. 4,847,755 is a processing system having a plurality of processor elements which analyzes instructions stream and adds intelligence to the instruction stream. For example, the system looks for natural concurrencies (independent instructions) and adds intelligence including a logical processor number and an instruction firing time to each instruction (column 17, lines 54-60), which essentially reorders the instructions. Logical resource drivers then (column 18, lines 10-25) deliver each instruction to the selected processing element.
U.S. Pat. No. 5,075,840 discusses a system with multiple processors which can execute instructions out of order. This system includes the capability to delay execution of a specific type of instruction until it can be executed in its appropriate sequential order.
It can be seen that none of the conventional systems provide a general solution to the problems associated with executing dependent instructions in a system having multiple execution units while preserving the sequence of all instructions. Many conventional systems, by executing instructions out of order, require a sophisticated branching mechanism which adds a great deal of complexity to the processing system. Thus, by preserving the order of the instructions the present invention optimizes performance by reducing overhead, e.g. determining when a branch will occur. It would be advantageous to have a processor that can operate with many types of computer systems wherein instructions are analyzed and executed based only on their dependencies with other instructions and not the capabilities of the execution units.